1. Field of the Invention
The present invention relates to an integrated circuit device and a method of fabricating the same, and more particularly to a self-aligned contact (SAC) and a two-step method of fabricating the same.
2. Description of Related Art
Along with the progress of science and technology, the integration of electronic devices must be improved to meet the trend of light, thin, short, and small electronic devices. In addition to reducing the size of the semiconductor devices, the method of improving the integration can also be achieved by reducing the distance between semiconductor devices. However, some process problems are unavoidable no matter the size of the semiconductor devices or the distance between the semiconductor devices is reduced.
As for a self-aligned contact process, after the contact is downsized, the aspect ratio of the contact is increased, such that the etching becomes difficult and the process window becomes small. In order to remove the residual in the etching process and keep contact hole open, a long time over-etching is usually performed to avoid that the contact hole cannot be fully opened. However, referring to FIG. 1, during a lithography process, misalignment often occurs, and a bowling effect often occurs when etching a dielectric layer 16 to form a contact hole 14. Therefore, if the over-etching takes a long time, a top corner 10 of a gate 12 may be exposed easily, resulting in a gate poly short problem, as shown in region A. In another aspect, as the aspect ratio of the contact hole increases, the filling of the metal layer in the contact hole becomes increasingly difficult.
US Patent Application NO. 2005/0136649 has disclosed a method of fabricating a self-aligned contact. First, a stacked film layer of a plurality of layers of different materials on a substrate. Then, an inner insulating layer is formed. Thereafter, a single-stage self-aligned contact etching process is performed in a source/drain region by utilizing different etching rates of individual film layers. During the process of removing the inner insulating layer and a portion of the stacked film layer, one film layer in the stack layer is used as an etch stop layer to form a contact hole with a T-shaped section, so as to expose the film layer used as the etch stop layer in the stacked film layer.
U.S. Pat. No. 6,791,190 has disclosed a method of fabricating a self-aligned contact. First, a conformal liner layer is formed on a substrate. An inner dielectric layer is formed. The inner dielectric layer is patterned with the conformal liner layer as an etch stop layer to form a self-aligned contact hole/borderless contact hole. The method also uses a single-stage self-aligned contact etching process to form the contact hole/borderless contact hole.
In another aspect, in a common semiconductor process, in order to increase the mobility of electrons or holes in channels of MOS transistor, a stress layer is usually formed on the substrate after fabricating the metal oxide semiconductor (MOS) transistor. As for a PMOS transistor, a stress layer having compressive stress is formed on the substrate, and generates a compressive stress along the channel direction in the PMOS transistor. As for an NMOS transistor, a stress layer having tensile stress is formed on the substrate, and generates a tensile stress along the channel direction in the NMOS transistor. Along with the increase of the compressive stress or tensile stress, the mobility of electrons or holes in the channel increases, thereby increasing the drive current to improve device performance.
Since the stress layer is very thick, the above problems and the problem of application area limiting on the source/drain region with larger area and lower accuracy still exist when performing etching process of the self-aligned contact with the above single step conventional methods.